1. Field of the Invention
The present invention relates to a technique for checking quality of a wiring. More particularly, the present invention relates to a technique for checking quality of wirings connecting a plurality of chips which are, for example, incorporated in a single package.
2. Description of the Background Art
There is a case that a plurality of semiconductor integrated circuit chips (hereinafter, simply referred to as “chips”) are incorporated into a single package. This package is, for example, referred to as a multichip module. For example, the multichip module can realize a SIP (System In a Package).
The multichip module has the wiring connecting the chips in the package. If any defectiveness is present in the wiring, the multichip module is a defective product regardless of quality of each chip.
Defectiveness of the wiring is detectable through a function test applied to all of the package. However, making clear the mutual relationship between function defectiveness and wiring defectiveness is not always easy. Furthermore, in some cases, producing a signal pattern used for detecting the wiring defectiveness may be difficult.
In view of the above, there is a conventional technique proposed for detecting the wiring defectiveness according to which an arbitrary signal is input from an input terminal group to the wiring and this signal is output via the wiring to an output terminal group. This kind of conventional technique is, for example, disclosed in the Japanese Patent Application Laid-open No. 2000-022072.
However, according to the technique disclosed in the above prior art document, transmission of the signal from the input terminal group to the output terminal group is parallel. Accordingly, numerous terminals are necessary to perform the quality test.